Controlling current leakage and power consumption through voltage drops (VD) across components can allow a designer to extended battery life for mobile computing devices as well as decrease heat generation in all devices. When using a Metal Oxide Semiconductor (MOS) device for gating power to a circuit, the device must be large enough that the voltage drop across the device in ON state does not impact the circuit performance. However, sometimes this comes at the expense of excess current leakage. Therefore, a device selected to be optimized to meet a target voltage drop requirement during active operation of one circuit is not optimal for all circuits. In designs of 65 nanometer spacing designs and smaller, current leakage can be a significant portion of an active power budget.